1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device that enables to realize finer contacts and interconnections.
2. Description of the Prior Art
In recent years, conductor contacts in a semiconductor device have been becoming slenderer and interconnections therein have been becoming narrower due to increase in the integration scale of components. Such the slenderized contacts and narrowed interconnections cause increase in not only contact resistance but also interconnection resistance. Therefore, it has become important for the semiconductor device to reduce the contact and interconnection resistances as low as possible.
To form the slenderized contacts, it is required that miniaturized (or small-diameter) contact holes are formed in an insulator layer and that the contact holes are filled with a conductor material so that uniform step coverage is obtained. Such the conductor contacts have been realized by a conventional "conductor plug" technique. In this technique, a conductor layer is formed on an interlayer insulator film to fill contact holes of the interlayer insulator film and then, the conductor layer is etched back to be left only in the contact holes as conductor plugs.
Also, to form the narrowed interconnections having a low resistance, a "self-aligned silicide" technique has been developed. In this technique, a metal layer is deposited on a patterned silicon layer and then, the metal layer reacts with the silicon layer to produce a metal silicide layer at their interface. The unreacted metal layer is then removed, resulting in a patterned metal silicide layer placed on the patterned metal layer in self-alignment.
FIGS. 1C to 1F show a conventional fabrication method of a semiconductor device, in which the above conductor plug and self-aligned silicide techniques are employed.
First, an impurity-doped region or diffusion region 22 is formed in the surface area of a silicon substrate 21 as a conductor layer. An interlayer insulator film 23 is then formed on the substrate 21 to cover the region 22. A patterned photoresist film 26 is formed on the interlayer insulator film 23 by a photolithography technique. Using the patterned photoresist film 26 as a mask, the interlayer insulator film 23 is selectively etched until the impurity-doped region 22 is exposed from the film 23 by a reactive ion etching technique, producing a penetrating contact hole 27 in the film 23. The state at this time is shown in FIG. 1A.
Next, after removing the photoresist film 26, a first phosphorus-doped polysilicon layer 28 is deposited on the entire interlayer insulator film 23 by a Low-Pressure Chemical Vapor Deposition (LPCVD) technique. During this CVD process, as shown in FIG. 1B, the contact hole 27 is filled with the phosphorus-doped polysilicon.
The first polysilicon layer 28 is then etched back entirely by a reactive ion etching technique to be left only in the contact hole 27, producing a polysilicon plug 29 in the hole 27, as shown in FIG. 1C. The bottom end of the plug 29 is contacted with the impurity-doped region 22 and the top end thereof is slightly lower than the surface of the interlayer insulator film 23.
A second phosphorus-doped polysilicon layer 24 is formed on the entire interlayer insulator film 23 by a LPCVD technique and then, a patterned photoresist film 30 is formed on the layer 24 by a photolithography technique. Using the patterned photoresist film 30 as a mask, the second polysilicon layer 24 is selectively etched by a reactive ion etching technique to be patterned to a desired interconnection shape, as shown in FIG. 1D.
After the photoresist film 30 is removed, a titanium (Ti) layer 31 is formed on the remaining second polysilicon layer 24 and the exposed interlayer insulator film 23 by a sputtering technique, as shown in FIG. 1E. Then, the two layers 31 and 24 are subjected to a heat-treatment to react with each other, producing selectively a titanium silicide (TiSi.sub.2) layer at the interface between the layers 31 and 24.
Finally, the unreacted titanium layer 31 and reaction products such as a titanium nitride (TiN) are removed, resulting in a patterned silicide layer 32 on the remaining polysilicon layer 24. Thus, the silicide layer 32 is selectively formed in self-alignment with the underlying polysilicon layer 24. The patterned polysilicon layer 24 and the patterned silicide layer 32, which form a polycide structure, constitute an interconnection or wiring 35 of the semiconductor device.
With the above-described conventional fabrication method, the following problems occur.
During the process step of forming the second polysilicon layer 24 (FIG. 1D), a native oxide layer 33 of SiO.sub.2 tends to be generated at the interface between the polysilicon plug 29 and the second polysilicon layer 24. The native oxide layer 33 is produced due to inadvertent oxidation of the plug 29 during the loading of the substrate 21 into a CVD chamber. The layer 33 causes the increase of the contact resistance between the plug 29 and the layer 24.
Also, during the process step of forming the plug 29 (FIG. 1C), the top of the first polysilicon layer 28 in the contact hole 27 is slightly overetched, resulting in the depression on the remaining polysilicon plug 29. Consequently, the second polysilicon layer 24 is contacted with the polysilicon plug 29 only at the top face of the plug 29.
Further, when the phosphorus concentration of the second polysilicon layer 24 is high, the contact resistance can be prevented from increasing. However, such the high phosphorus concentration decreases the silicide reaction rate so that the silicidation rate of titanium becomes low, making the TiSi2 layer 32 thinner. This results in the resistance increase of the interconnection 35.
On the other hand, when the phosphorus concentration of the second polysilicon layer 24 is low, the resistance of the interconnect 35 can be restrained. However, the resistance between the polysilicon plug 29 and the titanium silicide layer 32 increases because the second polysilicon layer 24 having the high resistance is provided therebetween. This also leads to the resistance increase of the interconnection 35.
The Japanese Non-Examined Patent Publication No. 3-185823, which was published in August 1991, discloses a measure to remove the native oxide layer 33. In this measure, although the native oxide layer 33 is effectively removed by a chemically dry etching process, another native oxide layer will be generated again due to exposure to the atmosphere or air after the chemically dry etching process. Therefore, this method does not provide a basic or fundamental solution for this problem.
To cancel or avoid the generation of the native oxide layer completely, the substrate 21 is essential to be loaded into a CVD chamber used for the formation of the second polysilicon layer 24 without exposure to the atmosphere (i.e., while keeping the vacuum condition) after the chemically dry etching process. This requires a very expensive multichamber equipment.